At the IEEE International Electron Devices Meeting (IEDM) 2019, Intel had two package integration presentations, one on its Omni-Directional Interconnect and one on its 3D stacking Foveros technology. In the first talk, one of Intel’s engineers presenting at the conference said a rather curious thing that hasn’t been previously disclosed.
One of the highlights of 2019 as a whole has been Intel’s disclosures about its new 3D stacking, or ‘Foveros’, technology. The idea here is that using multiple silicon dies stacked on top of each other, you can decrease the overall die size of a chip but also increase the bandwidth if one of the silicon dies is dedicated to cache or memory. In the case of Intel’s first Foveros chip, Lakefield, we have one IO die and one compute die on different process nodes stacked together with additional PoP memory on top of the stacked design. Lakefield has been announced for two products so far, the Samsung Galaxy Book S and the Microsoft Surface Neo, both of which are scheduled to come to market in mid-2020.
Intel’s second announced Foveros chip is its new Xe-HPC architecture based graphics card design for high performance computing. Given the code name ‘Ponte Vecchio’, the new GPU is slated for a late 2021 launch and will use Foveros technology to help build out compute performance across 8 compute dies per slide, and Ponte Vecchio will have two slices per GPU. This GPU is being built primarily for the exascale-class Aurora supercomputer, which is set to be installed in the Argonne National Laboratories in 2021.
So what was the off-hand comment made at IEDM this year? On stage, an Intel Principle Engineer stated that by Holiday 2020, we should expect to see a refresh of Lakefield in the market. The engineer did state that first generation of Lakefield was already in the market (albeit announced for products you can’t even pre-order yet), and that we should expect to see the second generation refresh by the end of 2020. At this point it is too easy to speculate what a refresh might be: with a stacked chip design one might assume a new IO die for next generation PCIe or something, or a new compute die with a rebalanced core / optimized core / better efficiency core. Unfortunately Intel didn’t elaborate.
Intel is betting on its new Foveros technology, as with its EMIB interconnects, as a corner stone of certain areas of its product portfolio as we roll into the new decade. It will be interesting to see if the cost can be amortized into more price-sensitive areas. During the same IEDM presentation, the same principle engineer also mentioned that the Foveros stacking technology can also lend itself to adding on a modem into that stack – given that Intel recently announced a partnership with Mediatek to provide 5G connectivity for its products, one can make the assumption that at some point we’ll see a Foveros product with a modem too.
Hopefully Intel will disclose more in the early part of 2020.